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version 1.1, 1998/01/18 11:11:49
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version 1.1.2.3, 1998/01/24 11:55:10
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/* |
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* Copyright 1996-1997 David J. McKay |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a |
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* copy of this software and associated documentation files (the "Software"), |
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* to deal in the Software without restriction, including without limitation |
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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* and/or sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF |
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvsetup.c,v 1.1.2.2 1998/01/24 00:04:41 robin Exp $ */ |
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#include <stdlib.h> |
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#include "nvuser.h" |
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#include "nv1ref.h" |
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#include "nvreg.h" |
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typedef struct { |
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UINT32 id; /* 32 bit unique identifer for this object */ |
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UINT32 channel; /* What channel this object belongs to */ |
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UINT32 context; /* Holds configuration of pipeline. Written to CTX SWITCH */ |
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}NVObject; |
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static int graphicsEngineOk; |
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#define WaitForIdle() while(PGRAPH_Read(STATUS)) |
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static void EnableOptimisations(void) |
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{ |
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/* Now switch on all the optimisations that there are */ |
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PGRAPH_Write(DEBUG_0,PGRAPH_Def(DEBUG_0_EDGE_FILLING,ENABLED) | |
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PGRAPH_Def(DEBUG_0_WRITE_ONLY_ROPS,ENABLED) | |
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PGRAPH_Def(DEBUG_0_NONBLOCK_BROAD,ENABLED) | |
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PGRAPH_Def(DEBUG_0_BLOCK_BROAD,ENABLED) | |
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PGRAPH_Def(DEBUG_0_BLOCK,ENABLED) | |
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PGRAPH_Def(DEBUG_0_BULK_READS,ENABLED)); |
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PGRAPH_Write(DEBUG_1,PGRAPH_Def(DEBUG_1_HIRES_TM,DISABLED) | |
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PGRAPH_Def(DEBUG_1_FAST_BUS,DISABLED) | |
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PGRAPH_Def(DEBUG_1_TM_QUAD_HANDOFF,ENABLED) | |
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PGRAPH_Def(DEBUG_1_FAST_RMW_BLITS,ENABLED) | |
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PGRAPH_Def(DEBUG_1_PATT_BLOCK,ENABLED) | |
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PGRAPH_Def(DEBUG_1_TRI_OPTS,DISABLED) | |
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PGRAPH_Def(DEBUG_1_BI_RECTS,DISABLED) | |
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PGRAPH_Def(DEBUG_1_DMA_ACTIVITY,IGNORE) | |
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PGRAPH_Def(DEBUG_1_VOLATILE_RESET,NOT_LAST)); |
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PGRAPH_Write(DEBUG_2,PGRAPH_Def(DEBUG_2_VOLATILE_RESET,ENABLED) | |
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PGRAPH_Def(DEBUG_2_TM_FASTINPUT,ENABLED) | |
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PGRAPH_Def(DEBUG_2_BUSY_PATIENCE,ENABLED) | |
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PGRAPH_Def(DEBUG_2_TRAPEZOID_TEXEL,ENABLED) | |
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PGRAPH_Def(DEBUG_2_MONO_ABORT,DISABLED) | |
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PGRAPH_Def(DEBUG_2_BETA_ABORT,ENABLED) | |
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PGRAPH_Def(DEBUG_2_ALPHA_ABORT,ENABLED) | |
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PGRAPH_Def(DEBUG_2_AVOID_RMW_BLEND,DISABLED)); |
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/* |
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* REV c parts have another debug register here, but ignore for the |
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* moment |
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*/ |
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} |
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static void InitDMAInstance(void) |
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{ |
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PDMA_Write(GR_CHANNEL,PDMA_Def(GR_CHANNEL_ACCESS,DISABLED)); |
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PDMA_Write(GR_INSTANCE,0); |
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PGRAPH_Write(DMA,0); |
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PGRAPH_Write(NOTIFY,0); |
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PDMA_Write(GR_CHANNEL,PDMA_Def(GR_CHANNEL_ACCESS,ENABLED)); |
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} |
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static void DisableFifo(void) |
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{ |
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/* Disable CACHE1 first */ |
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PFIFO_Write(CACHES,PFIFO_Def(CACHES_REASSIGN,DISABLED)); |
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PFIFO_Write(CACHE1_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,DISABLED)); |
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PFIFO_Write(CACHE1_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,DISABLED)); |
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PFIFO_Write(CACHE0_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,DISABLED)); |
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PFIFO_Write(CACHE0_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,DISABLED)); |
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} |
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static void EnableFifo(void) |
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{ |
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/* Enable CACHE1 first */ |
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PFIFO_Write(CACHE1_PUSH0,PFIFO_Def(CACHE1_PUSH0_ACCESS,ENABLED)); |
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PFIFO_Write(CACHE1_PULL0,PFIFO_Def(CACHE1_PULL0_ACCESS,ENABLED)); |
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PFIFO_Write(CACHES,PFIFO_Def(CACHES_REASSIGN,ENABLED)); |
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} |
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#define PRIV_RAM_SIZE 0 |
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#define NUM_FIFO_CONTEXT ((PRIV_RAM_SIZE)? 128 : 64) |
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/* Clear out channel 0 fifo context */ |
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static void ClearOutFifoContext(void) |
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{ |
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int i; |
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|
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/* Set up size of PRAM */ |
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PRAM_Write(CONFIG_0,PRAM_Val(CONFIG_0_SIZE,PRIV_RAM_SIZE)); |
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for(i=0;i<NUM_FIFO_CONTEXT;i++) { |
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nvPRAMFCPort[i]=0; |
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} |
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} |
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int NvKbRamUsedByHW(void) |
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{ |
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/* Audio scratch and password context are fixed at 4K, |
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* but hash table, runout and fifo vary with PRIV_RAM_SIZE |
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*/ |
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return ( (8<<PRIV_RAM_SIZE)+4 ); |
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} |
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static void ClearOutContext(void) |
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{ |
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int i; |
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/* Init context register */ |
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PGRAPH_Write(CTX_SWITCH,0); |
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ClearOutFifoContext(); |
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/* Set PUT and GET pointers to address 0*/ |
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PFIFO_Write(CACHE1_PUT,0);PFIFO_Write(CACHE1_GET,0); |
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/* Make sure there is no runout data */ |
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PFIFO_Write(RUNOUT_PUT,0); |
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PFIFO_Write(RUNOUT_GET,0); |
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/* Nobody is allowed to lie about how much space in the fifo */ |
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PFIFO_Write(CONFIG_0,PFIFO_Def(CONFIG_0_FREE_LIE,DISABLED)); |
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/* Clear out CACHED CONTEXT registers */ |
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for(i=0;i<NV_PFIFO_CACHE1_CTX__SIZE_1;i++) { |
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PFIFO_Write(CACHE1_CTX(i),0); |
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} |
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} |
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#define HASH_TABLE_DEPTH (2<<PRIV_RAM_SIZE) |
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#define HASH_TABLE_SIZE 256 |
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typedef struct { |
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UINT32 id; |
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UINT32 context; |
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}HashTableEntry; |
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static HashTableEntry localHash[HASH_TABLE_SIZE][HASH_TABLE_DEPTH]; |
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static HashTableEntry *realHash=NULL; |
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#define HASH_FIFO(h,c) ((((h)^((h)>>8)^((h)>>16)^((h)>>24))&0xFF)^((c)&0x7F)) |
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#define HASH_ENTRY(index,depth) (((index)*HASH_TABLE_DEPTH)+(depth)) |
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static void ClearOutHashTables(void) |
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{ |
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int i,j; |
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if(!realHash) realHash=(HashTableEntry *) nvPRAMHTPort; |
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/* Clear out host copy of hash table */ |
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for(i=0;i<HASH_TABLE_SIZE;i++) { |
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for(j=0;j<HASH_TABLE_DEPTH;j++) { |
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localHash[i][j].id=0; |
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localHash[i][j].context=0; |
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(realHash+HASH_ENTRY(i,j))->id=0; |
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(realHash+HASH_ENTRY(i,j))->context=0; |
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} |
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} |
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/* Clear out hash virtual registers */ |
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for(i=0;i<NV_PRAM_HASH_VIRTUAL__SIZE_1;i++) { |
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PRAM_Write(HASH_VIRTUAL(i),0); |
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} |
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} |
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/* Defaults the context for the channel to be something sensible. |
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* This code is the basis of what needs to be context switched if this |
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* driver ever expands to cope with multiple channels at the same time. |
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*/ |
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void LoadChannelContext(void) |
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{ |
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int i; |
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UINT32 read; |
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/* Force Cache 0 and Cache 1 to be set for channel 0 */ |
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PFIFO_Write(CACHE0_PUSH1,0); |
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PFIFO_Write(CACHE1_PUSH1,0); |
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PFIFO_Write(CACHE1_PULL1, 0); |
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read=PFIFO_Read(CACHE1_PULL1); |
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PFIFO_Write(CACHE1_PULL1,read|PFIFO_Def(CACHE1_PULL1_CTX,DIRTY)); |
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read=PFIFO_Read(CACHE1_PULL1); |
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PFIFO_Write(CACHE1_PULL1,read|PFIFO_Def(CACHE1_PULL1_OBJECT,CHANGED)); |
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/* Set context control. Don't enable channel yet */ |
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PGRAPH_Write(CTX_CONTROL,PGRAPH_Def(CTX_CONTROL_MINIMUM_TIME,2MS) | |
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PGRAPH_Def(CTX_CONTROL_TIME,EXPIRED) | |
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PGRAPH_Def(CTX_CONTROL_CHID,INVALID) | |
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PGRAPH_Def(CTX_CONTROL_SWITCHING,IDLE) | |
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PGRAPH_Def(CTX_CONTROL_DEVICE,ENABLED)); |
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PGRAPH_Write(CANVAS_MIN,0); |
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PGRAPH_Write(CANVAS_MAX,PACK_UINT16(MAX_UINT16,MAX_UINT16)); |
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PGRAPH_Write(CLIP_MISC,0); |
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PGRAPH_Write(CLIP0_MIN,0); |
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PGRAPH_Write(CLIP1_MIN,0); |
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PGRAPH_Write(CLIP0_MAX,0); |
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PGRAPH_Write(CLIP1_MAX,0); |
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PGRAPH_Write(CANVAS_MISC,PGRAPH_Def(CANVAS_MISC_DAC_BYPASS,DISABLED)| |
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PGRAPH_Def(CANVAS_MISC_DITHER,ENABLED)| |
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PGRAPH_Def(CANVAS_MISC_REPLICATE,ENABLED)); |
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PGRAPH_Write(SOURCE_COLOR,0); |
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PGRAPH_Write(MONO_COLOR0,0); |
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PGRAPH_Write(MONO_COLOR1,0); |
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PGRAPH_Write(ABS_UCLIP_XMIN,0); |
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PGRAPH_Write(ABS_UCLIP_YMIN,0); |
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PGRAPH_Write(ABS_UCLIP_XMAX,0); |
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PGRAPH_Write(ABS_UCLIP_YMAX,0); |
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/* Beta and Plane Mask */ |
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PGRAPH_Write(PLANE_MASK,0xffffffff); |
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PGRAPH_Write(BETA,0); |
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for(i=0;i<NV_PGRAPH_BETA_RAM__SIZE_1;i++) { |
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PGRAPH_Write(BETA_RAM(i),0); |
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} |
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for(i=0;i<NV_PGRAPH_ABS_X_RAM__SIZE_1;i++) { |
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PGRAPH_Write(ABS_X_RAM(i),0); |
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} |
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for(i=0;i<NV_PGRAPH_ABS_Y_RAM__SIZE_1;i++) { |
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PGRAPH_Write(ABS_Y_RAM(i),0); |
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} |
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PGRAPH_Write(ABS_ICLIP_XMAX,0);PGRAPH_Write(ABS_ICLIP_YMAX,0); |
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PGRAPH_Write(XY_LOGIC_MISC0,0);PGRAPH_Write(XY_LOGIC_MISC1,0); |
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PGRAPH_Write(X_MISC,0);PGRAPH_Write(Y_MISC,0); |
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PGRAPH_Write(SUBDIVIDE,0);PGRAPH_Write(EDGEFILL,0); |
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/* Pattern registers . Initialise to something sensible */ |
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PGRAPH_Write(PATT_COLOR0_0,0);PGRAPH_Write(PATT_COLOR0_1,0xff); |
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PGRAPH_Write(PATT_COLOR1_0,1);PGRAPH_Write(PATT_COLOR1_1,0xff); |
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PGRAPH_Write(PATTERN(0),0xffffffff);PGRAPH_Write(PATTERN(1),0xffffffff); |
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PGRAPH_Write(PATTERN_SHAPE,0); |
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/* Set the ROP to be COPY (Uses Microshaft raster op codes) */ |
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PGRAPH_Write(ROP3,0xcc); |
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PGRAPH_Write(EXCEPTIONS,0); |
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PGRAPH_Write(BIT33,0); |
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} |
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static void EnableFlowThru(void) |
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{ |
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/* Disable the fifo and the DMA engine, but keep flowthu enabled. |
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* This state is needed to actually access many of the registers |
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* in the graphics engine that we are going to set up |
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*/ |
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PGRAPH_Write(MISC,PGRAPH_Def(MISC_FLOWTHRU_WRITE,ENABLED) | |
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PGRAPH_Def(MISC_FLOWTHRU,ENABLED) | |
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PGRAPH_Def(MISC_FIFO_WRITE,ENABLED) | |
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PGRAPH_Def(MISC_FIFO,DISABLED) | |
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PGRAPH_Def(MISC_DMA_WRITE,ENABLED) | |
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PGRAPH_Def(MISC_DMA,DISABLED) | |
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PGRAPH_Def(MISC_CLASS_WRITE,ENABLED) | |
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PGRAPH_Val(MISC_CLASS, 0)); |
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} |
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/* Will need to define here what all this lot actually does */ |
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#define COLOR_CONTEXT_R5G5B5 0x0 |
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#define COLOR_CONTEXT_R8G8B8 0x1 |
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#define COLOR_CONTEXT_R10G10B10 0x2 |
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#define COLOR_CONTEXT_Y8 0x3 |
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#define COLOR_CONTEXT_Y16 0x4 |
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#define GENERATE_CONTEXT(device,cfg,chroma,plane,clip,color,alpha) \ |
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DEVICE_BASE(device)|\ |
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SetBF(4:0,cfg)|SetBF(5:5,chroma)|SetBF(6:6,plane)|\ |
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SetBF(7:7,clip)|SetBF(8:8,0)|SetBF(12:9,color)|\ |
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SetBF(13:13,alpha)|SetBF(14:14,0)|SetBF(15:15,0) |
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/* This value does SRC & PATTERN */ |
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/* The pattern is disabled/enabled by the ROP code we set up */ |
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#define PATCH_CONTEXT 0x10 |
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/* All contexts will be generated at run time as we need to set the color |
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* format dynamically |
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*/ |
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static NVObject ropObject; |
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static NVObject clipObject; |
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static NVObject patternObject; |
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static NVObject rectObject; |
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static NVObject blitObject; |
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static NVObject colourExpandObject; |
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static NVObject lineObject; |
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static NVObject linObject; |
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static NVObject chromaObject; |
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#define Info ErrorF |
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static void InitObject(NVObject *object) |
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{ |
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UINT32 hash; |
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int i; |
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/* Will put an entry into the hash table */ |
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hash=HASH_FIFO(object->id,object->channel); |
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for(i=0;i<HASH_TABLE_DEPTH;i++) { |
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if(localHash[hash][i].id==0) break; /* Found an empty slot!!! */ |
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/* is object already in cache? */ |
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if(localHash[hash][i].context==object->id) return; |
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} |
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if(i==HASH_TABLE_DEPTH) { |
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/* There is no room at the inn. Since we can't cope with reloading |
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* context we had better abort here!! |
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*/ |
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Info("**** NO ROOM FOR OBJECT %08lx IN HASH TABLE ****\n",object->id); |
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graphicsEngineOk=0; /* Set flag so that we won't use accel */ |
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return; |
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} |
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/* Ok, bung entry in at appropriate place */ |
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localHash[hash][i].id=object->id; |
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localHash[hash][i].context=object->context; |
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(realHash+HASH_ENTRY(hash,i))->id=object->id; |
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(realHash+HASH_ENTRY(hash,i))->context=object->context; |
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} |
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static void SetUpObjects(int bpp) |
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{ |
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int colorContext=(bpp==8) ? COLOR_CONTEXT_R8G8B8 : COLOR_CONTEXT_R5G5B5; |
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ropObject.id=ROP_OBJECT_ID; |
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ropObject.channel=0; |
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ropObject.context=GENERATE_CONTEXT(UROP,0,0,0,0,0,0); |
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InitObject(&ropObject); |
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clipObject.id=CLIP_OBJECT_ID; |
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clipObject.channel=0; |
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clipObject.context=GENERATE_CONTEXT(UCLIP,0,0,0,0,0,0); |
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InitObject(&clipObject); |
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|
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patternObject.id=PATTERN_OBJECT_ID; |
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patternObject.channel=0; |
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patternObject.context= |
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GENERATE_CONTEXT(UPATT,0,0,0,0,colorContext,0); |
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InitObject(&patternObject); |
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|
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rectObject.id=RECT_OBJECT_ID; |
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rectObject.channel=0; |
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rectObject.context= |
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GENERATE_CONTEXT(URECT,PATCH_CONTEXT,0,0,1,colorContext,0); |
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InitObject(&rectObject); |
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|
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|
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blitObject.id=BLIT_OBJECT_ID; |
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blitObject.channel=0; |
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blitObject.context= |
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GENERATE_CONTEXT(UBLIT,PATCH_CONTEXT,0,0,1,colorContext,0); |
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InitObject(&blitObject); |
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|
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colourExpandObject.id=COLOUR_EXPAND_OBJECT_ID; |
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colourExpandObject.channel=0; |
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colourExpandObject.context= |
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GENERATE_CONTEXT(UBITMAP,PATCH_CONTEXT,0,0,1,colorContext,1); |
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InitObject(&colourExpandObject); |
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|
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lineObject.id=LINE_OBJECT_ID; |
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lineObject.channel=0; |
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lineObject.context= |
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GENERATE_CONTEXT(ULINE,PATCH_CONTEXT,0,0,1,colorContext,0); |
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InitObject(&lineObject); |
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|
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linObject.id=LIN_OBJECT_ID; |
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linObject.channel=0; |
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linObject.context= |
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GENERATE_CONTEXT(ULIN,PATCH_CONTEXT,0,0,1,colorContext,0); |
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InitObject(&linObject); |
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} |
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|
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static void ClearAndEnableInterrupts(void) |
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{ |
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PGRAPH_Write(INTR_0,PGRAPH_Def(INTR_0_RESERVED,RESET)| |
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PGRAPH_Def(INTR_0_CONTEXT_SWITCH,RESET)| |
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PGRAPH_Def(INTR_0_VBLANK,RESET)| |
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PGRAPH_Def(INTR_0_RANGE,RESET)| |
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PGRAPH_Def(INTR_0_METHOD_COUNT,RESET)| |
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PGRAPH_Def(INTR_0_SOFTWARE,RESET)| |
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PGRAPH_Def(INTR_0_COMPLEX_CLIP,RESET)| |
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PGRAPH_Def(INTR_0_NOTIFY,RESET)); |
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|
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|
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/* Enable all interrupts except VBLANK */ |
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PGRAPH_Write(INTR_EN_0,PGRAPH_Def(INTR_EN_0_RESERVED,ENABLED)| |
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PGRAPH_Def(INTR_EN_0_CONTEXT_SWITCH,ENABLED)| |
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PGRAPH_Def(INTR_EN_0_VBLANK,DISABLED)| |
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PGRAPH_Def(INTR_EN_0_RANGE,ENABLED)| |
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PGRAPH_Def(INTR_EN_0_METHOD_COUNT,ENABLED)| |
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PGRAPH_Def(INTR_EN_0_SOFTWARE,ENABLED)| |
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PGRAPH_Def(INTR_EN_0_COMPLEX_CLIP,ENABLED)| |
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PGRAPH_Def(INTR_EN_0_NOTIFY,ENABLED)); |
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|
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PGRAPH_Write(INTR_1,PGRAPH_Def(INTR_1_METHOD,RESET)| |
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PGRAPH_Def(INTR_1_DATA,RESET)| |
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PGRAPH_Def(INTR_1_NOTIFY_INST,RESET)| |
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PGRAPH_Def(INTR_1_DOUBLE_NOTIFY,RESET)| |
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PGRAPH_Def(INTR_1_CTXSW_NOTIFY,RESET)); |
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|
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/* Don't care about any of this lot */ |
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PGRAPH_Write(INTR_EN_1,0); |
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|
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/* Reset the FIFO interrupt state */ |
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PFIFO_Write(INTR_0, PFIFO_Def(INTR_0_CACHE_ERROR,RESET)| |
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PFIFO_Def(INTR_0_RUNOUT,RESET)| |
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PFIFO_Def(INTR_0_RUNOUT_OVERFLOW,RESET)); |
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|
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PFIFO_Write(INTR_EN_0, PFIFO_Def(INTR_EN_0_CACHE_ERROR,ENABLED)| |
| |
PFIFO_Def(INTR_EN_0_RUNOUT,ENABLED)| |
| |
PFIFO_Def(INTR_EN_0_RUNOUT_OVERFLOW,ENABLED)); |
| |
|
| |
/* Switch on all the user devices in the master control */ |
| |
PMC_Write(ENABLE,PMC_Def(ENABLE_PAUDIO,ENABLED) | |
| |
PMC_Def(ENABLE_PDMA,ENABLED) | |
| |
PMC_Def(ENABLE_PFIFO,ENABLED) | |
| |
PMC_Def(ENABLE_PGRAPH,ENABLED) | |
| |
PMC_Def(ENABLE_PRM,ENABLED) | |
| |
PMC_Def(ENABLE_PFB,ENABLED)); |
| |
} |
| |
|
| |
static void ResetEngine(void) |
| |
{ |
| |
/* Reset the graphics engine state machine */ |
| |
PGRAPH_Write(DEBUG_1,PGRAPH_Def(DEBUG_1_VOLATILE_RESET,LAST)); |
| |
PGRAPH_Write(DEBUG_0,PGRAPH_Def(DEBUG_0_STATE,RESET)); |
| |
} |
| |
|
| |
static void EnableChannel(void) |
| |
{ |
| |
|
| |
/* Set context control */ |
| |
PGRAPH_Write(CTX_CONTROL,PGRAPH_Def(CTX_CONTROL_MINIMUM_TIME,2MS) | |
| |
PGRAPH_Def(CTX_CONTROL_TIME,EXPIRED) | |
| |
PGRAPH_Def(CTX_CONTROL_CHID,VALID) | |
| |
PGRAPH_Def(CTX_CONTROL_SWITCHING,IDLE) | |
| |
PGRAPH_Def(CTX_CONTROL_DEVICE,ENABLED)); |
| |
|
| |
|
| |
PGRAPH_Write(MISC,PGRAPH_Def(MISC_FLOWTHRU_WRITE,ENABLED) | |
| |
PGRAPH_Def(MISC_FLOWTHRU,ENABLED) | |
| |
PGRAPH_Def(MISC_FIFO_WRITE,ENABLED) | |
| |
PGRAPH_Def(MISC_FIFO,ENABLED) | |
| |
PGRAPH_Def(MISC_DMA_WRITE,ENABLED) | |
| |
PGRAPH_Def(MISC_DMA,ENABLED) | |
| |
PGRAPH_Def(MISC_CLASS_WRITE,IGNORED) | |
| |
PGRAPH_Val(MISC_CLASS, 0)); |
| |
} |
| |
|
| |
int SetupGraphicsEngine(int bpp) |
| |
{ |
| |
graphicsEngineOk=1; |
| |
|
| |
WaitForIdle(); |
| |
/* Possibly enable the hardware engines here. Should already be on though */ |
| |
|
| |
DisableFifo(); |
| |
|
| |
EnableFlowThru(); |
| |
|
| |
ResetEngine(); |
| |
|
| |
EnableOptimisations(); |
| |
|
| |
InitDMAInstance(); |
| |
|
| |
ClearAndEnableInterrupts(); |
| |
|
| |
ClearOutContext(); |
| |
|
| |
ClearOutHashTables(); |
| |
|
| |
LoadChannelContext(); |
| |
|
| |
SetUpObjects(bpp); |
| |
|
| |
EnableChannel(); |
| |
|
| |
EnableFifo(); |
| |
|
| |
return graphicsEngineOk; |
| |
|
| |
} |
| |
|
| |
static int channelOpen=0; |
| |
|
| |
NvChannel *NvOpenChannel(void) |
| |
{ |
| |
if(channelOpen) return NULL; |
| |
|
| |
channelOpen=1; |
| |
return (NvChannel*) nvCHAN0Port; |
| |
} |
| |
|
| |
/* Bit of future-proofing here */ |
| |
void NvCloseChannel(void) |
| |
{ |
| |
channelOpen=0; |
| |
} |
| |
|
| |
void NvSync(void) |
| |
{ |
| |
WaitForIdle(); |
| |
} |
| |
|
| |
/* This function checks to see if an interrupt has been raised, then |
| |
* prints out the appropriate registers so that you can attempt to |
| |
* figure out what is going on |
| |
* if you start mucking around with this chip this will happen a lot |
| |
*/ |
| |
|
| |
|
| |
|
| |
#define CheckBit(var,device,bitfield) \ |
| |
if(var & device##_Mask(bitfield)) {\ |
| |
Info(#device"_"#bitfield" Set\n");\ |
| |
} |
| |
|
| |
|
| |
void NvCheckForErrors(void) |
| |
{ |
| |
UINT32 val=PMC_Read(INTR_0); |
| |
/* Has an interrupt been raised ???? */ |
| |
/*if(val==0) return;*/ |
| |
/* Info("An Interrupt has been raised.\n");*/ |
| |
CheckBit(val,PMC,INTR_0_PAUDIO); |
| |
CheckBit(val,PMC,INTR_0_PDMA); |
| |
CheckBit(val,PMC,INTR_0_PFIFO); |
| |
CheckBit(val,PMC,INTR_0_PGRAPH); |
| |
CheckBit(val,PMC,INTR_0_PRM); |
| |
CheckBit(val,PMC,INTR_0_PTIMER); |
| |
CheckBit(val,PMC,INTR_0_PFB); |
| |
CheckBit(val,PMC,INTR_0_SOFTWARE); |
| |
|
| |
val=PGRAPH_Read(INTR_0); |
| |
CheckBit(val,PGRAPH,INTR_0_RESERVED); |
| |
CheckBit(val,PGRAPH,INTR_0_CONTEXT_SWITCH); |
| |
/* CheckBit(val,PGRAPH,INTR_0_VBLANK);*/ |
| |
CheckBit(val,PGRAPH,INTR_0_RANGE); |
| |
CheckBit(val,PGRAPH,INTR_0_METHOD_COUNT); |
| |
CheckBit(val,PGRAPH,INTR_0_SOFTWARE); |
| |
CheckBit(val,PGRAPH,INTR_0_COMPLEX_CLIP); |
| |
CheckBit(val,PGRAPH,INTR_0_NOTIFY); |
| |
|
| |
val=PFIFO_Read(INTR_0); |
| |
CheckBit(val,PFIFO,INTR_0_CACHE_ERROR); |
| |
CheckBit(val,PFIFO,INTR_0_RUNOUT); |
| |
CheckBit(val,PFIFO,INTR_0_RUNOUT_OVERFLOW); |
| |
} |
Return to
nvsetup.c
CVS log
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