xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/Attic/nvreg.h - diff

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Diff for /xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/Attic/nvreg.h between version 3.2 and 3.2.2.2

version 3.2, 1996/12/27 07:05:43

version 3.2.2.2, 1998/10/19 07:33:50

Line 1

/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */

/***************************************************************************\

|* *|

* Permission is hereby granted, free of charge, to any person obtaining a

|* NOTICE TO USER: The source code is copyrighted under U.S. and *|

* copy of this software and associated documentation files (the "Software"),

|* international laws. NVIDIA, Corp. of Sunnyvale, California owns *|

* to deal in the Software without restriction, including without limitation

|* the copyright and as design patents pending on the design and *|

* the rights to use, copy, modify, merge, publish, distribute, sublicense,

|* interface of the NV chips. Users and possessors of this source *|

* and/or sell copies of the Software, and to permit persons to whom the

|* code are hereby granted a nonexclusive, royalty-free copyright *|

* Software is furnished to do so, subject to the following conditions:

|* and design patent license to use this code in individual and *|

|* commercial software. *|

* The above copyright notice and this permission notice shall be included in

|* *|

* all copies or substantial portions of the Software.

|* Any use of this source code must include, in the user documenta- *|

|* tion and internal comments to the code, notices to the end user *|

* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

|* as follows: *|

* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

|* *|

* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

|* in the U.S. and foreign countries. *|

* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF

|* *|

* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

|* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *|

* SOFTWARE.

|* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *|

|* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *|

|* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *|

|* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *|

|* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *|

|* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *|

|* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *|

|* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *|

|* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *|

|* PERFORMANCE OF THIS SOURCE CODE. *|

|* *|

\***************************************************************************/

/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.1 1996/10/23 13:10:52 dawes Exp $ */

/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */

#ifndef __NVREG_H_

#define __NVREG_H_

#define NV_FRAME_BUFFER 0x01000000 /* Frame buffer is at this BYTE address*/

/* Little macro to construct bitmask for contiguous ranges of bits */

#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))

#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)

/* Frame buffer registers */

/* Macro to set specific bitfields (mask has to be a macro x:y) ! */

#define NV_PFB_BOOT_0 (0x600000/4)

#define SetBF(mask,value) ((value) << (0?mask))

#define NV_PFB_CONFIG_0 (0x600200/4)

#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )

#define NV_PFB_START (0x600400/4)

#define NV_PFB_HOR_FRONT_PORCH (0x600500/4)

#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \

#define NV_PFB_HOR_SYNC_WIDTH (0x600510/4)

| SetBF(mask,value)))

#define NV_PFB_HOR_BACK_PORCH (0x600520/4)

#define NV_PFB_HOR_DISP_WIDTH (0x600530/4)

#define DEVICE_BASE(device) (0?NV##_##device)

#define NV_PFB_VER_FRONT_PORCH (0x600540/4)

#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)

#define NV_PFB_VER_SYNC_WIDTH (0x600550/4)

#define NV_PFB_VER_BACK_PORCH (0x600560/4)

/* This is where we will have to have conditional compilation */

#define NV_PFB_VER_DISP_WIDTH (0x600570/4)

#define DEVICE_ACCESS(device,reg) \

nv##device##Port[((NV_##device##_##reg)-DEVICE_BASE(device))/4]

#define NV_PFB_BOOT_0_RAM_AMOUNT 1,0

#define NV_PFB_CONFIG_0_VERTICAL 0,0 /* 1 during blank */

#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)

#define NV_PFB_CONFIG_0_PIXEL_DEPTH 9,8

#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg)

#define NV_PFB_CONFIG_0_SCANLINE 20,20

#define DEVICE_PRINT(device,reg) \

#define NV_PFB_CONFIG_0_PCLK_VCLK_RATIO 26,24

ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))

#define NV_PFB_CONFIG_0_RESOLUTION 6,4

#define DEVICE_DEF(device,mask,value) \

SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)

/* Text mode config registers */

#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)

#define NV_PRM_CONFIG_0 (0x6c0200/4)

#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)

#define NV_MEMORY_TRACE (0x6c1f00/4)

#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value)

#define NV_PBUS_ACCESS (0x1200/4)

#define PDAC_Read(reg) DEVICE_READ(PDAC,reg)

#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg)

#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value)

/* Addreses for the DAC micro port */

#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value)

#define NV_DAC_WRITE_PALETTE (0x609000/4)

#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask)

#define NV_DAC_COLOUR_DATA (0x609004/4)

#define NV_DAC_PIXEL_MASK (0x609008/4)

#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value)

#define NV_DAC_READ_PALETTE (0x60900c/4)

#define PFB_Read(reg) DEVICE_READ(PFB,reg)

#define NV_DAC_INDEX_LO (0x609010/4)

#define PFB_Print(reg) DEVICE_PRINT(PFB,reg)

#define NV_DAC_INDEX_HI (0x609014/4)

#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value)

#define NV_DAC_INDEX_DATA (0x609018/4)

#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value)

#define NV_DAC_GAME_PORT (0x60901c/4)

#define PFB_Mask(mask) DEVICE_MASK(PFB,mask)

#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value)

/* Extended register values */

#define PRM_Read(reg) DEVICE_READ(PRM,reg)

#define NV_DAC_COMPANY_ID 0x00

#define PRM_Print(reg) DEVICE_PRINT(PRM,reg)

#define NV_DAC_DEVICE_ID 0x01

#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value)

#define NV_DAC_REVISION_ID 0x02

#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value)

#define NV_DAC_CONF_0 0x04

#define PRM_Mask(mask) DEVICE_MASK(PRM,mask)

#define NV_DAC_CONF_1 0x05

#define NV_DAC_RGB_PAL_CTRL 0x09

#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value)

#define NV_DAC_VPLL_M_PARAM 0x18

#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg)

#define NV_DAC_VPLL_N_PARAM 0x19

#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg)

#define NV_DAC_VPLL_O_PARAM 0x1a

#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value)

#define NV_DAC_VPLL_P_PARAM 0x1b

#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value)

#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask)

#define NV_DAC_CONF_0_IDC_MODE 5,5

#define NV_DAC_CONF_0_VGA_STATE 4,4

#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)

#define NV_DAC_CONF_0_PORT_WIDTH 3,2

#define PDMA_Read(reg) DEVICE_READ(PDMA,reg)

#define NV_DAC_CONF_0_VISUAL_DEPTH 1,0

#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)

#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)

#define NV_DAC_CONF_1_VCLK_IMPEDANCE 3,3

#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)

#define NV_DAC_CONF_1_PCLK_VCLK_RATIO 2,0

#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)

#define NV_DAC_SGS_ID 0x44

#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value)

#define NV_DAC_1764_ID 0x64

#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg)

#define NV_DAC_1732_ID 0x32

#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg)

#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value)

#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value)

#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask)

#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value)

#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg)

#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg)

#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value)

#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value)

#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask)

#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)

#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)

#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)

#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)

#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)

#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)

#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value)

#define PRAM_Read(reg) DEVICE_READ(PRAM,reg)

#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg)

#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value)

#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value)

#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask)

#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value)

#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg)

#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg)

#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value)

#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value)

#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask)

#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)

#define PMC_Read(reg) DEVICE_READ(PMC,reg)

#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)

#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)

#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)

#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)

#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)

#define PMC_Read(reg) DEVICE_READ(PMC,reg)

#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)

#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)

#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)

#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)

#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value)

#define PBUS_Read(reg) DEVICE_READ(PBUS,reg)

#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg)

#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value)

#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value)

#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask)

#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value)

#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg)

#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg)

#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value)

#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value)

#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask)

#define PDAC_ReadExt(reg) \

((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\

(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\

(PDAC_Read(INDEX_DATA)))

#define PDAC_WriteExt(reg,value)\

((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\

(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\

(PDAC_Write(INDEX_DATA,(value))))

#define CRTC_Write(index,value) outb(0x3d4,(index));outb(0x3d5,value)

#define CRTC_Read(index) (outb(0x3d4,index),inb(0x3d5))

#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value)

#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index)

#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)

#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)

#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)

#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value)

#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5))

/* These are the variables which actually point at the register blocks */

extern volatile unsigned *nvPDACPort; /* Points to the DAC */

extern volatile unsigned *nvPFBPort; /* Points to the Frame buffer */

extern volatile unsigned *nvPRMPort; /* Points to real mode stuff */

extern volatile unsigned *nvPGRAPHPort; /* Graphics unit */

extern volatile unsigned *nvPDMAPort; /* DMA engine */

extern volatile unsigned *nvPFIFOPort; /* FIFO registers */

extern volatile unsigned *nvPTIMERPort; /* TIMER registers */

extern volatile unsigned *nvPEXTDEVPort; /* EXTDEV registers */

extern volatile unsigned *nvPRAMPort; /* Priviliged RAM registers */

extern volatile unsigned *nvPRAMFCPort; /* Priviliged RAM (Fifo) */

extern volatile unsigned *nvPRAMHTPort; /* Priviliged RAM (hash) */

extern volatile unsigned *nvPMCPort; /* Priviliged RAM (hash) */

extern volatile unsigned *nvCHAN0Port; /* User channel 0 */

extern volatile unsigned *nvPRAMDACPort; /* Points to the RAMDAC */

extern volatile unsigned *nvPRAMINPort; /* Privileges instance memory */

extern volatile unsigned *nvPBUSPort; /* Priviled Bus */

extern volatile unsigned *nvPNVMPort; /* Priviled Bus */

extern volatile unsigned *dumb; /* FrameBuffer - hack!!!! */

typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType;

/* This points at the base of the memory mapped for the NV1

NVChipType GetChipType(void);

* Note that it is an int pointer, all writes must be 32 bit

extern volatile int *nvPort;

#define ReadExtReg(reg) \

((nvPort[NV_DAC_INDEX_LO] = (reg) & 0xff),\

(nvPort[NV_DAC_INDEX_HI] = ((reg) >> 8) & 0xff),\

(nvPort[NV_DAC_INDEX_DATA] & 0xff))

#define WriteExtReg(reg,value)\

nvPort[NV_DAC_INDEX_LO] = (reg) & 0xff,\

nvPort[NV_DAC_INDEX_HI] = ((reg) >> 8) & 0xff,\

nvPort[NV_DAC_INDEX_DATA] = ((value) & 0xff)

/* Little macro to construct bitmask for contiguous ranges of bits */

#define BITFIELDMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))

#define LOW_VALUE_OF_BITFIELDMASK(t,b) (b)

/* Macro to set specific bitfields (mask has to be a macro x,y) ! */

#define SETBITFIELD(var,mask,value) var=((var) & (~BITFIELDMASK(mask))) | \

((value) << LOW_VALUE_OF_BITFIELDMASK(mask))

#define GETBITFIELD(var,mask) (((unsigned)((var) & BITFIELDMASK(mask))) \

>> LOW_VALUE_OF_BITFIELDMASK(mask))

#endif

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