1 hohndel 1.1.2.1 /***************************************************************************\
2 |* *|
3 |* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *|
4 |* *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
9 |* *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
12 |* as follows: *|
13 |* *|
14 |* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *|
15 |* *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 hohndel 1.1.2.1 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27 |* *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
37 |* *|
38 \***************************************************************************/
|
40 hohndel 1.1.2.1 #include "nv4arb.h"
41 #include "nv4ref.h"
42 #include "nvreg.h"
43 static void CalcArbitration
44 (
45 fifo_info *fifo,
46 sim_state *arb
47 )
48 {
49 int data, m,n,p, pagemiss, cas,width, video_enable, color_key_enable, bpp, align;
50 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
51 int found, mclk_extra, mclk_loop, cbs, m1, p1;
52 int xtal_freq, mclk_freq, pclk_freq, nvclk_freq, mp_enable;
53 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
54 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
55 int craw, vraw;
56
57 fifo->valid = 1;
58 pclk_freq = arb->pclk_khz;
59 mclk_freq = arb->mclk_khz;
60 nvclk_freq = arb->nvclk_khz;
61 hohndel 1.1.2.1 pagemiss = arb->mem_page_miss;
62 cas = arb->mem_latency;
63 width = arb->memory_width >> 6;
64 video_enable = arb->enable_video;
65 color_key_enable = arb->gr_during_vid;
66 bpp = arb->pix_bpp;
67 align = arb->mem_aligned;
68 mp_enable = arb->enable_mp;
69 clwm = 0;
70 vlwm = 0;
71 cbs = 128;
72 pclks = 2;
73 nvclks = 2;
74 nvclks += 2;
75 nvclks += 1;
76 mclks = 5;
77 mclks += 3;
78 mclks += 1;
79 mclks += cas;
80 mclks += 1;
81 mclks += 1;
82 hohndel 1.1.2.1 mclks += 1;
83 mclks += 1;
84 mclk_extra = 3;
85 nvclks += 2;
86 nvclks += 1;
87 nvclks += 1;
88 nvclks += 1;
89 if (mp_enable)
90 mclks+=4;
91 nvclks += 0;
92 pclks += 0;
93 found = 0;
94 while (found != 1)
95 {
96 fifo->valid = 1;
97 found = 1;
98 mclk_loop = mclks+mclk_extra;
99 us_m = mclk_loop *1000*1000 / mclk_freq;
100 us_n = nvclks*1000*1000 / nvclk_freq;
101 us_p = nvclks*1000*1000 / pclk_freq;
102 if (video_enable)
103 hohndel 1.1.2.1 {
104 video_drain_rate = pclk_freq * 2;
105 crtc_drain_rate = pclk_freq * bpp/8;
106 vpagemiss = 2;
107 vpagemiss += 1;
108 crtpagemiss = 2;
109 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
110 if (nvclk_freq * 2 > mclk_freq * width)
111 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
112 else
113 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
114 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
115 vlwm = us_video * video_drain_rate/(1000*1000);
116 vlwm++;
117 vbs = 128;
118 if (vlwm > 128) vbs = 64;
119 if (vlwm > (256-64)) vbs = 32;
120 if (nvclk_freq * 2 > mclk_freq * width)
121 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
122 else
123 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
124 hohndel 1.1.2.1 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
125 us_crt =
126 us_video
127 +video_fill_us
128 +cpm_us
129 +us_m + us_n +us_p
130 ;
131 clwm = us_crt * crtc_drain_rate/(1000*1000);
132 clwm++;
133 }
134 else
135 {
136 crtc_drain_rate = pclk_freq * bpp/8;
137 crtpagemiss = 2;
138 crtpagemiss += 1;
139 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
140 us_crt = cpm_us + us_m + us_n + us_p ;
141 clwm = us_crt * crtc_drain_rate/(1000*1000);
142 clwm++;
143 }
144 m1 = clwm + cbs - 512;
145 hohndel 1.1.2.1 p1 = m1 * pclk_freq / mclk_freq;
146 p1 = p1 * bpp / 8;
147 if ((p1 < m1) && (m1 > 0))
148 {
149 fifo->valid = 0;
150 found = 0;
151 if (mclk_extra ==0) found = 1;
152 mclk_extra--;
153 }
154 else if (video_enable)
155 {
156 if ((clwm > 511) || (vlwm > 255))
157 {
158 fifo->valid = 0;
159 found = 0;
160 if (mclk_extra ==0) found = 1;
161 mclk_extra--;
162 }
163 }
164 else
165 {
166 hohndel 1.1.2.1 if (clwm > 519)
167 {
168 fifo->valid = 0;
169 found = 0;
170 if (mclk_extra ==0) found = 1;
171 mclk_extra--;
172 }
173 }
174 craw = clwm;
175 vraw = vlwm;
176 if (clwm < 384) clwm = 384;
177 if (vlwm < 128) vlwm = 128;
178 data = (int)(clwm);
179 fifo->graphics_lwm = data;
180 fifo->graphics_burst_size = 128;
181 data = (int)((vlwm+15));
182 fifo->video_lwm = data;
183 fifo->video_burst_size = vbs;
184 }
185 }
186 void nv4UpdateArbitrationSettings
187 hohndel 1.1.2.1 (
188 unsigned int VClk,
189 unsigned int pixelDepth,
190 unsigned int crystal,
191 unsigned char *lwm,
192 unsigned char *burst
193 )
194 {
195 fifo_info fifo_data;
196 sim_state sim_data;
197 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
198
199 pll = PRAMDAC_Read(MPLL_COEFF);
200 M = (pll >> 0) & 0xFF;
201 N = (pll >> 8) & 0xFF;
202 P = (pll >> 16) & 0x0F;
203 MClk = (N * crystal / M) >> P;
204 pll = PRAMDAC_Read(NVPLL_COEFF);
205 M = (pll >> 0) & 0xFF;
206 N = (pll >> 8) & 0xFF;
207 P = (pll >> 16) & 0x0F;
208 hohndel 1.1.2.1 NVClk = (N * crystal / M) >> P;
209 cfg1 = PFB_Read(CONFIG_1);
210 sim_data.pix_bpp = (char)pixelDepth;
211 sim_data.enable_video = 0;
212 sim_data.enable_mp = 0;
213 sim_data.memory_width = (PEXTDEV_Read(BOOT_0) & 0x10) ? 128 : 64;
214 sim_data.mem_latency = (char)cfg1 & 0x0F;
215 sim_data.mem_aligned = 1;
216 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) &0x01));
217 sim_data.gr_during_vid = 0;
218 sim_data.pclk_khz = VClk;
219 sim_data.mclk_khz = MClk;
220 sim_data.nvclk_khz = NVClk;
221 CalcArbitration(&fifo_data, &sim_data);
222 if (fifo_data.valid)
223 {
224 /*
225 *vlwm = fifo_data.video_lwm >> 1;
226 REG_WR32(NV_PVIDEO_FIFO_THRES, fifo_data.video_lwm >> 1);
227 switch (fifo_data.video_burst_size)
228 {
229 hohndel 1.1.2.1 case 128:
230 *vburst = 3;
231 REG_WR32(NV_PVIDEO_FIFO_BURST, 3);
232 break;
233 case 64:
234 *vburst = 2;
235 break;
236 case 32:
237 *vburst = 1;
238 break;
239 }
240 CRTC_WR(NV_CIO_CRE_FFLWM__INDEX, fifo_data.graphics_lwm >> 3);
241 */
242 *lwm = fifo_data.graphics_lwm >> 3;
243 switch (fifo_data.graphics_burst_size)
244 {
245 case 256:
246 *burst = 4;
247 /* CRTC_WR(NV_CIO_CRE_FF_INDEX, 4);*/
248 break;
249 case 128:
250 hohndel 1.1.2.1 *burst = 3;
251 break;
252 case 64:
253 *burst = 2;
254 break;
255 case 32:
256 *burst = 1;
257 break;
258 case 16:
259 *burst = 0;
260 break;
261 }
262 }
263 }
264
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