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version 1.1, 1998/10/19 07:33:44
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version 1.1.2.1, 1998/10/19 07:33:44
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/***************************************************************************\ |
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|* *| |
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|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| |
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|* *| |
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *| |
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|* international laws. Users and possessors of this source code are *| |
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|* hereby granted a nonexclusive, royalty-free copyright license to *| |
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|* use this code in individual and commercial software. *| |
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|* *| |
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|* Any use of this source code must include, in the user documenta- *| |
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|* tion and internal comments to the code, notices to the end user *| |
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|* as follows: *| |
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|* *| |
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|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| |
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|* *| |
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|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| |
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|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| |
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|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| |
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|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| |
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|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| |
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|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| |
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|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| |
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|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| |
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|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| |
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|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| |
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|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| |
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|* *| |
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|* U.S. Government End Users. This source code is a "commercial *| |
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|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| |
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|* consisting of "commercial computer software" and "commercial *| |
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|* computer software documentation," as such terms are used in *| |
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|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| |
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|* ment only as a commercial end item. Consistent with 48 C.F.R. *| |
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|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| |
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|* all U.S. Government End Users acquire the source code with only *| |
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|* those rights set forth herein. *| |
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|* *| |
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\***************************************************************************/ |
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#include "nv4arb.h" |
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#include "nv4ref.h" |
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#include "nvreg.h" |
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static void CalcArbitration |
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( |
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fifo_info *fifo, |
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sim_state *arb |
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) |
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{ |
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int data, m,n,p, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; |
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int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; |
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int found, mclk_extra, mclk_loop, cbs, m1, p1; |
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int xtal_freq, mclk_freq, pclk_freq, nvclk_freq, mp_enable; |
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int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; |
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int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm; |
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int craw, vraw; |
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|
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fifo->valid = 1; |
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pclk_freq = arb->pclk_khz; |
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mclk_freq = arb->mclk_khz; |
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nvclk_freq = arb->nvclk_khz; |
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pagemiss = arb->mem_page_miss; |
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cas = arb->mem_latency; |
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width = arb->memory_width >> 6; |
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video_enable = arb->enable_video; |
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color_key_enable = arb->gr_during_vid; |
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bpp = arb->pix_bpp; |
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align = arb->mem_aligned; |
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mp_enable = arb->enable_mp; |
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clwm = 0; |
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vlwm = 0; |
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cbs = 128; |
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pclks = 2; |
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nvclks = 2; |
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nvclks += 2; |
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nvclks += 1; |
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mclks = 5; |
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mclks += 3; |
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mclks += 1; |
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mclks += cas; |
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mclks += 1; |
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mclks += 1; |
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mclks += 1; |
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mclks += 1; |
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mclk_extra = 3; |
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nvclks += 2; |
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nvclks += 1; |
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nvclks += 1; |
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nvclks += 1; |
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if (mp_enable) |
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mclks+=4; |
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nvclks += 0; |
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pclks += 0; |
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found = 0; |
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while (found != 1) |
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{ |
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fifo->valid = 1; |
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found = 1; |
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mclk_loop = mclks+mclk_extra; |
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us_m = mclk_loop *1000*1000 / mclk_freq; |
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us_n = nvclks*1000*1000 / nvclk_freq; |
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us_p = nvclks*1000*1000 / pclk_freq; |
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if (video_enable) |
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{ |
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video_drain_rate = pclk_freq * 2; |
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crtc_drain_rate = pclk_freq * bpp/8; |
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vpagemiss = 2; |
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vpagemiss += 1; |
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crtpagemiss = 2; |
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vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; |
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if (nvclk_freq * 2 > mclk_freq * width) |
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video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ; |
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else |
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video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; |
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us_video = vpm_us + us_m + us_n + us_p + video_fill_us; |
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vlwm = us_video * video_drain_rate/(1000*1000); |
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vlwm++; |
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vbs = 128; |
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if (vlwm > 128) vbs = 64; |
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if (vlwm > (256-64)) vbs = 32; |
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if (nvclk_freq * 2 > mclk_freq * width) |
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video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ; |
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else |
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video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; |
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cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; |
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us_crt = |
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us_video |
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+video_fill_us |
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+cpm_us |
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+us_m + us_n +us_p |
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; |
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clwm = us_crt * crtc_drain_rate/(1000*1000); |
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clwm++; |
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} |
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else |
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{ |
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crtc_drain_rate = pclk_freq * bpp/8; |
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crtpagemiss = 2; |
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crtpagemiss += 1; |
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cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; |
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us_crt = cpm_us + us_m + us_n + us_p ; |
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clwm = us_crt * crtc_drain_rate/(1000*1000); |
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clwm++; |
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} |
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m1 = clwm + cbs - 512; |
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p1 = m1 * pclk_freq / mclk_freq; |
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p1 = p1 * bpp / 8; |
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if ((p1 < m1) && (m1 > 0)) |
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{ |
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fifo->valid = 0; |
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found = 0; |
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if (mclk_extra ==0) found = 1; |
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mclk_extra--; |
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} |
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else if (video_enable) |
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{ |
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if ((clwm > 511) || (vlwm > 255)) |
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{ |
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fifo->valid = 0; |
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found = 0; |
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if (mclk_extra ==0) found = 1; |
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mclk_extra--; |
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} |
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} |
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else |
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{ |
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if (clwm > 519) |
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{ |
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fifo->valid = 0; |
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found = 0; |
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if (mclk_extra ==0) found = 1; |
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mclk_extra--; |
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} |
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} |
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craw = clwm; |
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vraw = vlwm; |
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if (clwm < 384) clwm = 384; |
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if (vlwm < 128) vlwm = 128; |
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data = (int)(clwm); |
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fifo->graphics_lwm = data; |
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fifo->graphics_burst_size = 128; |
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data = (int)((vlwm+15)); |
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fifo->video_lwm = data; |
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fifo->video_burst_size = vbs; |
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} |
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} |
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void nv4UpdateArbitrationSettings |
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( |
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unsigned int VClk, |
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unsigned int pixelDepth, |
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unsigned int crystal, |
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unsigned char *lwm, |
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unsigned char *burst |
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) |
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{ |
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fifo_info fifo_data; |
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sim_state sim_data; |
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unsigned int M, N, P, pll, MClk, NVClk, cfg1; |
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|
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pll = PRAMDAC_Read(MPLL_COEFF); |
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M = (pll >> 0) & 0xFF; |
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N = (pll >> 8) & 0xFF; |
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P = (pll >> 16) & 0x0F; |
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MClk = (N * crystal / M) >> P; |
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pll = PRAMDAC_Read(NVPLL_COEFF); |
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M = (pll >> 0) & 0xFF; |
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N = (pll >> 8) & 0xFF; |
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P = (pll >> 16) & 0x0F; |
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NVClk = (N * crystal / M) >> P; |
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cfg1 = PFB_Read(CONFIG_1); |
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sim_data.pix_bpp = (char)pixelDepth; |
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sim_data.enable_video = 0; |
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sim_data.enable_mp = 0; |
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sim_data.memory_width = (PEXTDEV_Read(BOOT_0) & 0x10) ? 128 : 64; |
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sim_data.mem_latency = (char)cfg1 & 0x0F; |
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sim_data.mem_aligned = 1; |
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sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) &0x01)); |
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sim_data.gr_during_vid = 0; |
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sim_data.pclk_khz = VClk; |
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sim_data.mclk_khz = MClk; |
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sim_data.nvclk_khz = NVClk; |
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CalcArbitration(&fifo_data, &sim_data); |
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if (fifo_data.valid) |
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{ |
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/* |
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*vlwm = fifo_data.video_lwm >> 1; |
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REG_WR32(NV_PVIDEO_FIFO_THRES, fifo_data.video_lwm >> 1); |
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switch (fifo_data.video_burst_size) |
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{ |
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case 128: |
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*vburst = 3; |
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REG_WR32(NV_PVIDEO_FIFO_BURST, 3); |
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break; |
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case 64: |
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*vburst = 2; |
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break; |
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case 32: |
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*vburst = 1; |
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break; |
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} |
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CRTC_WR(NV_CIO_CRE_FFLWM__INDEX, fifo_data.graphics_lwm >> 3); |
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*/ |
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*lwm = fifo_data.graphics_lwm >> 3; |
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switch (fifo_data.graphics_burst_size) |
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{ |
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case 256: |
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*burst = 4; |
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/* CRTC_WR(NV_CIO_CRE_FF_INDEX, 4);*/ |
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break; |
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case 128: |
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*burst = 3; |
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break; |
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case 64: |
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*burst = 2; |
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break; |
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case 32: |
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*burst = 1; |
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break; |
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case 16: |
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*burst = 0; |
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break; |
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} |
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} |
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} |
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