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Diff for /xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/Attic/nv3driver.c between version 1.1.2.5 and 1.1.2.6

version 1.1.2.5, 1998/10/23 04:30:11 version 1.1.2.6, 1998/11/18 16:38:45
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  * SOFTWARE.  * SOFTWARE.
  */  */
  
 /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3driver.c,v 1.1.2.4 1998/10/19 07:33:40 hohndel Exp $ */  /* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nv3driver.c,v 1.1.2.5 1998/10/23 04:30:11 hohndel Exp $ */
  /***************************************************************************\  /***************************************************************************\
 |*                                                                           *| |*                                                                           *|
 |*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *| |*       Copyright 1993-1998 NVIDIA, Corporation.  All rights reserved.      *|
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 #include "extensions/xf86dgastr.h" #include "extensions/xf86dgastr.h"
 #endif #endif
  
 #include "nv3ref.h"  
 #include "nvcursor.h" #include "nvcursor.h"
 #include "nvreg.h" #include "nvreg.h"
  
  
 #include "nvvga.h" #include "nvvga.h"
  
 /*  
  * Some quick hacks for bandwidth/DAC calculations.  
  */  
 #define BUFFER_SGRAM    0  
 #define BUFFER_SDRAM    1  
 static unsigned ramType, crystalFreq; static unsigned ramType, crystalFreq;
  
 void NV3EnterLeave(Bool enter) void NV3EnterLeave(Bool enter)
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   if(enter) {   if(enter) {
     xf86EnableIOPorts(vga256InfoRec.scrnIndex);     xf86EnableIOPorts(vga256InfoRec.scrnIndex);
     outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5);      outb(vgaIOBase + 4, 17); temp = inb(vgaIOBase + 5);
     outb(vgaIOBase + 5, temp & 0x7F);      outb(vgaIOBase + 5, temp & 127);
     SR_Write(LOCK_EXT_INDEX,UNLOCK_EXT_MAGIC);      outb(964,( 6  ));outb(965, 87  ) ;
   }else {   }else {
     outb(vgaIOBase + 4, 0x11); temp = inb(vgaIOBase + 5);      outb(vgaIOBase + 4, 17); temp = inb(vgaIOBase + 5);
     outb(vgaIOBase + 5, (temp & 0x7F) | 0x80);      outb(vgaIOBase + 5, (temp & 127) | 128);
     SR_Write(LOCK_EXT_INDEX,LOCK_EXT_MAGIC);      outb(964,( 6  ));outb(965, 153  ) ;
     xf86DisableIOPorts(vga256InfoRec.scrnIndex);     xf86DisableIOPorts(vga256InfoRec.scrnIndex);
   }   }
 } }
  
 #define MapDevice(device,base) \  
   nv##device##Port=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex,\  
                                  MMIO_REGION,\  
                                  ((char*)(base))+DEVICE_BASE(device),\  
                                  DEVICE_SIZE(device))  
  
  
 static void MapNV3Regs(void *regBase,void *frameBase) static void MapNV3Regs(void *regBase,void *frameBase)
 { {
   MapDevice(PRAMDAC,regBase);    nvPRAMDACPort=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex, 3 , ((char*)( regBase ))+ (6815744) , ((6819839) - (6815744) +1) ) ;
   MapDevice(PFB,regBase);    nvPFBPort=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex, 3 , ((char*)( regBase ))+ (1048576) , ((1052671) - (1048576) +1) ) ;
   MapDevice(PFIFO,regBase);    nvPFIFOPort=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex, 3 , ((char*)( regBase ))+ (8192) , ((16383) - (8192) +1) ) ;
   MapDevice(PGRAPH,regBase);    nvPGRAPHPort=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex, 3 , ((char*)( regBase ))+ (4194304) , ((4202495) - (4194304) +1) ) ;
   MapDevice(PTIMER,regBase);    nvPTIMERPort=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex, 3 , ((char*)( regBase ))+ (36864) , ((40959) - (36864) +1) ) ;
   MapDevice(PEXTDEV,regBase);    nvPEXTDEVPort=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex, 3 , ((char*)( regBase ))+ (1052672) , ((1056767) - (1052672) +1) ) ;
   MapDevice(PMC,regBase);    nvPMCPort=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex, 3 , ((char*)( regBase ))+ (0) , ((4095) - (0) +1) ) ;
   MapDevice(CHAN0,regBase);    nvCHAN0Port=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex, 3 , ((char*)( regBase ))+ (8388608) , ((8454143) - (8388608) +1) ) ;
   MapDevice(PRAMIN,frameBase);    nvPRAMINPort=(unsigned*)xf86MapVidMem(vga256InfoRec.scrnIndex, 3 , ((char*)( frameBase ))+ (12582912) , ((16777215) - (12582912) +1) ) ;
 } }
  
 #define NV3_MAX_CLOCK_IN_KHZ 230000  
  
 static void NV3FlipFunctions(vgaVideoChipRec *nv); static void NV3FlipFunctions(vgaVideoChipRec *nv);
  
 int NV3Probe(vgaVideoChipRec *nv,void *base0,void *base1) int NV3Probe(vgaVideoChipRec *nv,void *base0,void *base1)
 { {
   int boot0, chipRev, chipSubrev;   int boot0, chipRev, chipSubrev;
   int noaccel= OFLG_ISSET(OPTION_NOACCEL,&vga256InfoRec.options);    int noaccel= (( &vga256InfoRec.options )->flag_bits[( 60  )/ (8 * sizeof(CARD32)) ] & (1 << (( 60  )% (8 * sizeof(CARD32)) ))) ;
  
   MapNV3Regs(base0,base1);   MapNV3Regs(base0,base1);
  
   /* Don't rely on user to specify RAM amount. */  
   boot0      = PFB_Read(BOOT_0);  
   chipRev    = PMC_Read(BOOT_0) & 0xF0;  
   chipSubrev = PMC_Read(BOOT_0) & 0x0F;  
   crystalFreq= (PEXTDEV_Read(BOOT_0) & PEXTDEV_Def(BOOT_0_STRAP_CRYSTAL, 14318180)) ? 14318 : 13500;  
  
   if (boot0 & PFB_Def(BOOT_0_RAM_AMOUNT_EXTENSION, 8MB))    boot0      = nvPFBPort[((1048576    )- (1048576) )/4]   ;
     chipRev    = nvPMCPort[((0    )- (0) )/4]    & 240;
     chipSubrev = nvPMCPort[((0    )- (0) )/4]    & 15;
     crystalFreq= (nvPEXTDEVPort[((1052672    )- (1052672) )/4]    & (( 1    ) << (6))   ) ? 14318 : 13500;
   
     if (boot0 & (( 1    ) << (5))   )
   {   {
       if ((chipRev == NV3_REV_C_00) && (chipSubrev >= NV_PMC_BOOT_0_FIB_REVISION_2))        if ((chipRev == 32 ) && (chipSubrev >= 2 ))
       {       {
           ramType = BUFFER_SDRAM;            ramType = 1 ;
           switch (boot0 & 0x03)            switch (boot0 & 3)
           {           {
               case NV_PFB_BOOT_0_RAM_AMOUNT_8MB:                case 0 :
               case NV_PFB_BOOT_0_RAM_AMOUNT_UNDEFINED:                case 3 :
                   vga256InfoRec.videoRam = 1024 * 8;                   vga256InfoRec.videoRam = 1024 * 8;
                   break;                   break;
               case NV_PFB_BOOT_0_RAM_AMOUNT_4MB:                case 2 :
                   vga256InfoRec.videoRam = 1024 * 4;                   vga256InfoRec.videoRam = 1024 * 4;
                   break;                   break;
               case NV_PFB_BOOT_0_RAM_AMOUNT_2MB:                case 1 :
               default:               default:
                   vga256InfoRec.videoRam = 1024 * 2;                   vga256InfoRec.videoRam = 1024 * 2;
                   break;                   break;
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       }       }
       else       else
       {       {
           ramType = BUFFER_SGRAM;            ramType = 0 ;
           vga256InfoRec.videoRam = 1024 * 8;           vga256InfoRec.videoRam = 1024 * 8;
       }       }
   }   }
   else   else
   {   {
       ramType = BUFFER_SGRAM;        ramType = 0 ;
  
       switch (boot0 & 0x03)        switch (boot0 & 3)
       {       {
           case NV_PFB_BOOT_0_RAM_AMOUNT_8MB:            case 0 :
               vga256InfoRec.videoRam = 1024 * 8;               vga256InfoRec.videoRam = 1024 * 8;
               break;               break;
           case NV_PFB_BOOT_0_RAM_AMOUNT_4MB:            case 2 :
               vga256InfoRec.videoRam = 1024 * 4;               vga256InfoRec.videoRam = 1024 * 4;
               break;               break;
           case NV_PFB_BOOT_0_RAM_AMOUNT_2MB:            case 1 :
           case NV_PFB_BOOT_0_RAM_AMOUNT_UNDEFINED:            case 3 :
               vga256InfoRec.videoRam = 1024 * 2;               vga256InfoRec.videoRam = 1024 * 2;
               break;               break;
       }       }
   }   }
  
   /* By the time we have got here, we know it is an NV3 */  
   vga256InfoRec.maxClock = NV3_MAX_CLOCK_IN_KHZ;    vga256InfoRec.maxClock = 230000 ;
  
   nv->ChipLinearSize=vga256InfoRec.videoRam*1024;   nv->ChipLinearSize=vga256InfoRec.videoRam*1024;
   /* Doesn't feel right that this should be an int! */  
   nv->ChipLinearBase=(int)base1;   nv->ChipLinearBase=(int)base1;
   nv->ChipHas32bpp=TRUE;    nv->ChipHas32bpp= 1 ;
   /* I/O ports are needed for things like pallete selection etc */  
   xf86ClearIOPortList (vga256InfoRec.scrnIndex);   xf86ClearIOPortList (vga256InfoRec.scrnIndex);
   xf86AddIOPorts(vga256InfoRec.scrnIndex,Num_VGA_IOPorts,VGA_IOPorts);   xf86AddIOPorts(vga256InfoRec.scrnIndex,Num_VGA_IOPorts,VGA_IOPorts);
   xf86EnableIOPorts(vga256InfoRec.scrnIndex);   xf86EnableIOPorts(vga256InfoRec.scrnIndex);
   vgaIOBase = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0;    vgaIOBase = (inb(972) & 1) ? 976 : 944;
   NV3EnterLeave(ENTER);    NV3EnterLeave(1 );
   
  
   /* The NV1 only supports 555 weighting, so force it here */  
   if(vgaBitsPerPixel==16 && !noaccel) {   if(vgaBitsPerPixel==16 && !noaccel) {
     ErrorF("%s %s: %s: Setting RGB weight to 555\n",XCONFIG_PROBED,      ErrorF("%s %s: %s: Setting RGB weight to 555\n","(--)" ,
                                                     vga256InfoRec.name,                                                     vga256InfoRec.name,
                                                     vga256InfoRec.chipset);                                                     vga256InfoRec.chipset);
     xf86weight.green=xf86weight.blue=xf86weight.red=5;     xf86weight.green=xf86weight.blue=xf86weight.red=5;
   }   }
  
   OFLG_SET(OPTION_NOACCEL, &(nv->ChipOptionFlags));    ((  &(nv->ChipOptionFlags) )->flag_bits[( 60  )/ (8 * sizeof(CARD32)) ] |= (1 << (( 60  )% (8 * sizeof(CARD32)) ))) ;
   OFLG_SET(OPTION_SW_CURSOR, &(nv->ChipOptionFlags));    ((  &(nv->ChipOptionFlags) )->flag_bits[( 62  )/ (8 * sizeof(CARD32)) ] |= (1 << (( 62  )% (8 * sizeof(CARD32)) ))) ;
  
   NV3FlipFunctions(nv);   NV3FlipFunctions(nv);
  
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     unsigned O;     unsigned O;
     unsigned P;     unsigned P;
  
     /*  
      * Calc VPLL.  
      */  
     DeltaOld = 0xFFFFFFFF;      DeltaOld = -1;
     VClk     = (unsigned)clockIn;     VClk     = (unsigned)clockIn;
     if (crystalFreq == 14318)     if (crystalFreq == 14318)
     {     {
         /* 14.3Khz */  
         lowM  = 8;         lowM  = 8;
         highM = 13;         highM = 13;
     }     }
     else     else
     {     {
         /* 13.5Khz */  
         lowM  = 7;         lowM  = 7;
         highM = 12;         highM = 12;
     }     }
     /*  
      * Calculate frequencies using KHz to keep the math precision inside 32 bits.  
      */  
     for (P = 0; P <= 3; P ++)     for (P = 0; P <= 3; P ++)
     {     {
         Freq = VClk << P;         Freq = VClk << P;
         /*  
          * Bound the parameters to the internal frequencies of the DAC.  
          */  
         if ((Freq >= 128000) && (Freq <= 230000))         if ((Freq >= 128000) && (Freq <= 230000))
         {         {
             for (M = lowM; M <= highM; M++)             for (M = lowM; M <= highM; M++)
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                     DeltaNew = VClk - Freq;                     DeltaNew = VClk - Freq;
                 if (DeltaNew < DeltaOld)                 if (DeltaNew < DeltaOld)
                 {                 {
                     /*  
                      * Closer match.  
                      */  
                     *mOut     = M;                     *mOut     = M;
                     *nOut     = N;                     *nOut     = N;
                     *pOut     = P;                     *pOut     = P;
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             }             }
         }         }
     }     }
     return (DeltaOld != 0xFFFFFFFF);      return (DeltaOld != -1);
 } }
  
 /* Very useful macro that allows you to set overflow bits */  
 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))  
 #define SetBit(n) (1<<(n))  
 #define Set8Bits(value) ((value)&0xff)  
  
 static int CalculateCRTC(DisplayModePtr mode) static int CalculateCRTC(DisplayModePtr mode)
 { {
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       vertEnd = mode->CrtcVSyncEnd - 1,       vertEnd = mode->CrtcVSyncEnd - 1,
       vertTotal = mode->CrtcVTotal - 2;       vertTotal = mode->CrtcVTotal - 2;
  
   /* Calculate correct value for offset register */  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x13]=((vga256InfoRec.displayWidth/8)*bpp)&0xff;    ((vgaNVPtr)vgaNewVideoState)->std.CRTC[19]=((vga256InfoRec.displayWidth/8)*bpp)&255;
   /* Extra bits for CRTC offset register */  
   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.repaint0=   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.repaint0=
     SetBitField((vga256InfoRec.displayWidth/8)*bpp,10:8,7:5);      (( (((unsigned)((  (vga256InfoRec.displayWidth/8)*bpp  ) & (((unsigned)(1U << ((( 10)-( 8)+1)))-1)  << ( 8))  )) >> (8) )  ) << (5))  ;
   
   
   
   
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0]= (( horizTotal - 4 )&255) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[1]= (( horizDisplay )&255) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[2]= (( horizDisplay )&255) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[3]= (( (((unsigned)((  horizTotal  ) & (((unsigned)(1U << ((( 4)-( 0)+1)))-1)  << ( 0))  )) >> (0) )  ) << (0))   | (1<<( 7 )) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[4]= (( horizStart )&255) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[5]= (( (((unsigned)((  horizTotal  ) & (((unsigned)(1U << ((( 5)-( 5)+1)))-1)  << ( 5))  )) >> (5) )  ) << (7))  |
                        (( (((unsigned)((  horizEnd  ) & (((unsigned)(1U << ((( 4)-( 0)+1)))-1)  << ( 0))  )) >> (0) )  ) << (0))  ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[6]= (( (((unsigned)((  vertTotal  ) & (((unsigned)(1U << ((( 7)-( 0)+1)))-1)  << ( 0))  )) >> (0) )  ) << (0))  ;
   
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[7]= (( (((unsigned)((  vertTotal  ) & (((unsigned)(1U << ((( 8)-( 8)+1)))-1)  << ( 8))  )) >> (8) )  ) << (0))  |
                        (( (((unsigned)((  vertDisplay  ) & (((unsigned)(1U << ((( 8)-( 8)+1)))-1)  << ( 8))  )) >> (8) )  ) << (1))  |
                        (( (((unsigned)((  vertStart  ) & (((unsigned)(1U << ((( 8)-( 8)+1)))-1)  << ( 8))  )) >> (8) )  ) << (2))  |
                        (( (((unsigned)((  vertDisplay  ) & (((unsigned)(1U << ((( 8)-( 8)+1)))-1)  << ( 8))  )) >> (8) )  ) << (3))  |
                        (1<<( 4 )) |
                        (( (((unsigned)((  vertTotal  ) & (((unsigned)(1U << ((( 9)-( 9)+1)))-1)  << ( 9))  )) >> (9) )  ) << (5))  |
                        (( (((unsigned)((  vertDisplay  ) & (((unsigned)(1U << ((( 9)-( 9)+1)))-1)  << ( 9))  )) >> (9) )  ) << (6))  |
                        (( (((unsigned)((  vertStart  ) & (((unsigned)(1U << ((( 9)-( 9)+1)))-1)  << ( 9))  )) >> (9) )  ) << (7))  ;
   
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[9]= (( (((unsigned)((  vertDisplay  ) & (((unsigned)(1U << ((( 9)-( 9)+1)))-1)  << ( 9))  )) >> (9) )  ) << (5))   | (1<<( 6 )) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[16]= (( vertStart )&255) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[17]= (( (((unsigned)((  vertEnd  ) & (((unsigned)(1U << ((( 3)-( 0)+1)))-1)  << ( 0))  )) >> (0) )  ) << (0))   | (1<<( 5 )) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[18]= (( vertDisplay )&255) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[21]= (( vertDisplay )&255) ;
     ((vgaNVPtr)vgaNewVideoState)->std.CRTC[22]= (( vertTotal + 1 )&255) ;
   
     ((vgaNVPtr)vgaNewVideoState)->regs.nv3.screenExtra= (( (((unsigned)((  horizTotal  ) & (((unsigned)(1U << ((( 6)-( 6)+1)))-1)  << ( 6))  )) >> (6) )  ) << (4))   |
                                (( (((unsigned)((  vertDisplay  ) & (((unsigned)(1U << ((( 10)-( 10)+1)))-1)  << ( 10))  )) >> (10) )  ) << (3))   |
                                (( (((unsigned)((  vertStart  ) & (((unsigned)(1U << ((( 10)-( 10)+1)))-1)  << ( 10))  )) >> (10) )  ) << (2))   |
                                (( (((unsigned)((  vertDisplay  ) & (((unsigned)(1U << ((( 10)-( 10)+1)))-1)  << ( 10))  )) >> (10) )  ) << (1))   |
                                (( (((unsigned)((  vertTotal  ) & (((unsigned)(1U << ((( 10)-( 10)+1)))-1)  << ( 10))  )) >> (10) )  ) << (0))  ;
   
     if(mode->Flags & 32 ) ((vgaNVPtr)vgaNewVideoState)->std.CRTC[9]|=128;
   
   
   
  
   /* The NV3 manuals states that for native modes, there should be no  
    * borders. This code should also be tidied up to use symbolic names  
    */  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x0]=Set8Bits(horizTotal - 4);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x1]=Set8Bits(horizDisplay);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x2]=Set8Bits(horizDisplay);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x3]=SetBitField(horizTotal,4:0,4:0) | SetBit(7);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x4]=Set8Bits(horizStart);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x5]=SetBitField(horizTotal,5:5,7:7)|  
                      SetBitField(horizEnd,4:0,4:0);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x6]=SetBitField(vertTotal,7:0,7:0);  
   
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x7]=SetBitField(vertTotal,8:8,0:0)|  
                      SetBitField(vertDisplay,8:8,1:1)|  
                      SetBitField(vertStart,8:8,2:2)|  
                      SetBitField(vertDisplay,8:8,3:3)|  
                      SetBit(4)|  
                      SetBitField(vertTotal,9:9,5:5)|  
                      SetBitField(vertDisplay,9:9,6:6)|  
                      SetBitField(vertStart,9:9,7:7);  
   
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x9]= SetBitField(vertDisplay,9:9,5:5) | SetBit(6);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x10]= Set8Bits(vertStart);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x11]= SetBitField(vertEnd,3:0,3:0) | SetBit(5);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x12]= Set8Bits(vertDisplay);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x15]= Set8Bits(vertDisplay);  
   ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x16]= Set8Bits(vertTotal + 1);  
   
   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.screenExtra= SetBitField(horizTotal,6:6,4:4) |  
                              SetBitField(vertDisplay,10:10,3:3) |  
                              SetBitField(vertStart,10:10,2:2) |  
                              SetBitField(vertDisplay,10:10,1:1) |  
                              SetBitField(vertTotal,10:10,0:0);  
   
   if(mode->Flags & V_DBLSCAN) ((vgaNVPtr)vgaNewVideoState)->std.CRTC[0x9]|=0x80;  
   
   /* I think this should be SetBitField(horizTotal,8:8,0:0), but this  
    * doesn't work apparently. Why 260 ? 256 would make sense.  
    */  
   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.horizExtra= (horizTotal < 260 ? 0 : 1);   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.horizExtra= (horizTotal < 260 ? 0 : 1);
   return 1;   return 1;
 } }
  
 /* Gamma seems possible only for 15bpp and 32bpp. Need to fiddle  
  * around to confirm this  
  */  
 #define GammaMode() (!(vgaBitsPerPixel==8 || xf86weight.green==6))  
  
 static void InitPalette(DisplayModePtr mode) static void InitPalette(DisplayModePtr mode)
 { {
   int bpp=vgaBitsPerPixel/8;   int bpp=vgaBitsPerPixel/8;
   int i;   int i;
  
   if(!GammaMode()) return;    if(! (!(vgaBitsPerPixel==8 || xf86weight.green==6)) ) return;
   /* Put simple ramp in for now !! */  
   /* Do any other drivers implement gamma ?? */  
   for(i=0;i<256;i++) {   for(i=0;i<256;i++) {
     ((vgaNVPtr)vgaNewVideoState)->std.DAC[i*3]=i>>2;     ((vgaNVPtr)vgaNewVideoState)->std.DAC[i*3]=i>>2;
     ((vgaNVPtr)vgaNewVideoState)->std.DAC[(i*3)+1]=i>>2;     ((vgaNVPtr)vgaNewVideoState)->std.DAC[(i*3)+1]=i>>2;
Line 392 
Line 386 
   int i;   int i;
   int pixelDepth;   int pixelDepth;
  
   /* Calculate standard VGA settings */  
   if(!vgaHWInit (mode, sizeof (vgaNVRec))) {   if(!vgaHWInit (mode, sizeof (vgaNVRec))) {
     return 0;     return 0;
   }   }
   /* VGA is always valid for the NV3 */  
   ((vgaNVPtr)vgaNewVideoState)->vgaValid=1;   ((vgaNVPtr)vgaNewVideoState)->vgaValid=1;
   /* Calculate Vclock frequency */  
   if(!NV3ClockSelect(clockIn,&clockOut,&m,&n,&p)) {   if(!NV3ClockSelect(clockIn,&clockOut,&m,&n,&p)) {
     ErrorF("%s %s: %s: Unable to set desired video clock\n",     ErrorF("%s %s: %s: Unable to set desired video clock\n",
            XCONFIG_PROBED, vga256InfoRec.name,vga256InfoRec.chipset);             "(--)" , vga256InfoRec.name,vga256InfoRec.chipset);
     return FALSE;      return 0 ;
   }   }
   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.vpllCoeff=PRAMDAC_Val(VPLL_COEFF_NDIV,n) |    ((vgaNVPtr)vgaNewVideoState)->regs.nv3.vpllCoeff= ((   n   ) << (8))    |
                           PRAMDAC_Val(VPLL_COEFF_MDIV,m) |                            ((   m   ) << (0))    |
                           PRAMDAC_Val(VPLL_COEFF_PDIV,p);                            ((   p   ) << (16))   ;
  
   CalculateCRTC(mode);   CalculateCRTC(mode);
   InitPalette(mode);   InitPalette(mode);
   /* For now I don't support 8 bit pallettes but it is easy to add */  
   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.repaint1=   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.repaint1=
     PCRTC_Val(REPAINT1_LARGE_SCREEN,mode->CrtcHDisplay<1280) |      ((   mode->CrtcHDisplay<1280   ) << (2))    |
     PCRTC_Def(REPAINT1_PALETTE_WIDTH,6BITS);      (( 1    ) << (1))   ;
   /* PixelFormat controls how many bits per pixel.  
    * There is another register in the  
    * DAC which controls if mode is 5:5:5 or 5:6:5  
    */  
   pixelDepth=(vgaBitsPerPixel+1)/8;   pixelDepth=(vgaBitsPerPixel+1)/8;
   if(pixelDepth>3) pixelDepth=3;   if(pixelDepth>3) pixelDepth=3;
   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.pixelFormat=pixelDepth;   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.pixelFormat=pixelDepth;
  
   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.generalControl=   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.generalControl=
      PRAMDAC_Def(GENERAL_CONTROL_IDC_MODE,GAMMA)|       (( 0    ) << (4))   |
      PRAMDAC_Val(GENERAL_CONTROL_565_MODE,xf86weight.green==6)|       ((   xf86weight.green==6   ) << (12))   |
      PRAMDAC_Def(GENERAL_CONTROL_TERMINATION,37OHM)|       (( 0    ) << (17))   |
      PRAMDAC_Def(GENERAL_CONTROL_BPC,6BITS)|       (( 0    ) << (20))   |
      PRAMDAC_Def(GENERAL_CONTROL_VGA_STATE,SEL); /* Not sure about this */       (( 1    ) << (8))   ;
   /*  
    * Calculate video arbitration values.  This is a black box full of scary things.  Don't look.  
    */  
   nv3UpdateArbitrationSettings((unsigned int)clockOut,   nv3UpdateArbitrationSettings((unsigned int)clockOut,
                                pixelDepth*8,                                pixelDepth*8,
                                crystalFreq,                                crystalFreq,
                               &(((vgaNVPtr)vgaNewVideoState)->regs.nv3.fifo),                               &(((vgaNVPtr)vgaNewVideoState)->regs.nv3.fifo),
                               &(((vgaNVPtr)vgaNewVideoState)->regs.nv3.fifoControl));                               &(((vgaNVPtr)vgaNewVideoState)->regs.nv3.fifoControl));
   /*  
    * This makes sure that the Mclock and Vclock are are actually selected  
    * via the PLL. It also sets the Vclock/Pclock ratio to be divide by 2  
    * or not. Not sure when this should be divide by 1, presumably for  
    * very high Vclock????  
    */  
   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.coeffSelect=PRAMDAC_Def(PLL_COEFF_SELECT_MPLL_SOURCE,PROG)    ((vgaNVPtr)vgaNewVideoState)->regs.nv3.coeffSelect= (( 1    ) << (8))
                                                     |PRAMDAC_Def(PLL_COEFF_SELECT_VPLL_SOURCE,PROG)                                                      | (( 1    ) << (16))
                                                     |PRAMDAC_Def(PLL_COEFF_SELECT_VCLK_RATIO,DB2);                                                      | (( 1    ) << (28))   ;
   /*  
    * Only divide when outputting to TV.  Just don't do it.  
    */  
   /* Disable Tetris tiling for now. This looks completely mad but could  
    * give some significant performance gains. Will perhaps experiment  
    * later on with this stuff!  
    */  
   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.config0=   ((vgaNVPtr)vgaNewVideoState)->regs.nv3.config0=
       PFB_Val(CONFIG_0_RESOLUTION,((vga256InfoRec.displayWidth+31)/32))|        ((   ((vga256InfoRec.displayWidth+31)/32)   ) << (0))   |
       PFB_Val(CONFIG_0_PIXEL_DEPTH,pixelDepth)|        ((   pixelDepth   ) << (8))   |
       PFB_Def(CONFIG_0_TILING,DISABLED);        (( 1    ) << (12))   ;
  
   return TRUE;    return 1 ;
 } }
  
 static void NV3Restore(void *data) static void NV3Restore(void *data)
Line 465 
Line 459 
   vgaNVPtr restore=data;   vgaNVPtr restore=data;
   NV3Registers *nv3=&(restore->regs.nv3);   NV3Registers *nv3=&(restore->regs.nv3);
  
   /*  
    * Instance memory should also be restored here.  
    */  
   vgaProtect(TRUE);    vgaProtect(1 );
   vgaHWRestore((vgaHWPtr)restore);   vgaHWRestore((vgaHWPtr)restore);
   PCRTC_Write(REPAINT0,nv3->repaint0);    outb(980,( 25   ));outb(981,  nv3->repaint0  )  ;
   PCRTC_Write(REPAINT1,nv3->repaint1);    outb(980,( 26   ));outb(981,  nv3->repaint1  )  ;
   PCRTC_Write(EXTRA,nv3->screenExtra);    outb(980,( 37   ));outb(981,  nv3->screenExtra  )  ;
   PCRTC_Write(PIXEL,nv3->pixelFormat);    outb(980,( 40   ));outb(981,  nv3->pixelFormat  )  ;
   PCRTC_Write(HORIZ_EXTRA,nv3->horizExtra);    outb(980,( 45   ));outb(981,  nv3->horizExtra  )  ;
   PCRTC_Write(FIFO_CONTROL,nv3->fifoControl);    outb(980,( 27   ));outb(981,  nv3->fifoControl  )  ;
   PCRTC_Write(FIFO,nv3->fifo);    outb(980,( 32   ));outb(981,  nv3->fifo  )  ;
   PFB_Write(CONFIG_0,nv3->config0);    nvPFBPort[((1049088    )- (1048576) )/4] =(  nv3->config0  )  ;
   PRAMDAC_Write(VPLL_COEFF,nv3->vpllCoeff);    nvPRAMDACPort[((6817032    )- (6815744) )/4] =(  nv3->vpllCoeff  )  ;
   PRAMDAC_Write(PLL_COEFF_SELECT,nv3->coeffSelect);    nvPRAMDACPort[((6817036    )- (6815744) )/4] =(  nv3->coeffSelect  )  ;
   PRAMDAC_Write(GENERAL_CONTROL,nv3->generalControl);    nvPRAMDACPort[((6817280    )- (6815744) )/4] =(  nv3->generalControl  )  ;
   vgaProtect(FALSE);    vgaProtect(0 );
 } }
  
 static void *NV3Save(void *data) static void *NV3Save(void *data)
 { {
   vgaNVPtr save=NULL;    vgaNVPtr save= ((void *)0) ;
  
   save=(vgaNVPtr)vgaHWSave((vgaHWPtr)data,sizeof(vgaNVRec));   save=(vgaNVPtr)vgaHWSave((vgaHWPtr)data,sizeof(vgaNVRec));
   save->regs.nv3.repaint0=PCRTC_Read(REPAINT0);    save->regs.nv3.repaint0= (outb(980, 25   ),inb(981))  ;
   save->regs.nv3.repaint1=PCRTC_Read(REPAINT1);    save->regs.nv3.repaint1= (outb(980, 26   ),inb(981))  ;
   save->regs.nv3.screenExtra=PCRTC_Read(EXTRA);    save->regs.nv3.screenExtra= (outb(980, 37   ),inb(981))  ;
   save->regs.nv3.pixelFormat=PCRTC_Read(PIXEL);    save->regs.nv3.pixelFormat= (outb(980, 40   ),inb(981))  ;
   save->regs.nv3.horizExtra=PCRTC_Read(HORIZ_EXTRA);    save->regs.nv3.horizExtra= (outb(980, 45   ),inb(981))  ;
   save->regs.nv3.fifoControl=PCRTC_Read(FIFO_CONTROL);    save->regs.nv3.fifoControl= (outb(980, 27   ),inb(981))  ;
   save->regs.nv3.fifo=PCRTC_Read(FIFO);    save->regs.nv3.fifo= (outb(980, 32   ),inb(981))  ;
   save->regs.nv3.config0=PFB_Read(CONFIG_0);    save->regs.nv3.config0= nvPFBPort[((1049088    )- (1048576) )/4]   ;
   save->regs.nv3.vpllCoeff=PRAMDAC_Read(VPLL_COEFF);    save->regs.nv3.vpllCoeff= nvPRAMDACPort[((6817032    )- (6815744) )/4]   ;
   save->regs.nv3.coeffSelect=PRAMDAC_Read(PLL_COEFF_SELECT);    save->regs.nv3.coeffSelect= nvPRAMDACPort[((6817036    )- (6815744) )/4]   ;
   save->regs.nv3.generalControl=PRAMDAC_Read(GENERAL_CONTROL);    save->regs.nv3.generalControl= nvPRAMDACPort[((6817280    )- (6815744) )/4]   ;
  
   return (void*)save;   return (void*)save;
 } }
Line 512 
Line 506 
   int pan=(startAddr&3)*2;   int pan=(startAddr&3)*2;
   unsigned char byte;   unsigned char byte;
  
   /* Now shift start address. Word aligned */  
   CRTC_Write(0x0d,Set8Bits(offset));    outb(980,( 13 ));outb(981, (( offset )&255)  ) ;
   CRTC_Write(0x0c,SetBitField(offset,15:8,7:0));    outb(980,( 12 ));outb(981, (( (((unsigned)((  offset  ) & (((unsigned)(1U << ((( 15)-( 8)+1)))-1)  << ( 8))  )) >> (8) )  ) << (0))   ) ;
   byte=PCRTC_Read(REPAINT0) & ~PCRTC_Mask(REPAINT0_START_ADDR_20_16);    byte= (outb(980, 25   ),inb(981))   & ~(((unsigned)(1U << ((( 4)-( 0)+1)))-1)  << ( 0))    ;
   PCRTC_Write(REPAINT0,SetBitField(offset,20:16,4:0)|byte);    outb(980,( 25   ));outb(981,  (( (((unsigned)((  offset  ) & (((unsigned)(1U << ((( 20)-( 16)+1)))-1)  << ( 16))  )) >> (16) )  ) << (0))  |byte  )  ;
   /* Attribute register 0x13 is used to provide up to 4 pixel shift */  
   byte=inb(vgaIOBase+0x0a);    byte=inb(vgaIOBase+10);
   outb(0x3c0,0x13);    outb(960,19);
   outb(0x3c0,pan);    outb(960,pan);
 } }
  
 /*  
  * Because we have such a fast DAC, the video stream can saturate the bandwidth of  
  * slower memories.  Kill modes that use too much bandwidth.  
  */  
 static int NV3ValidMode(DisplayModePtr mode,Bool verbose,int flag) static int NV3ValidMode(DisplayModePtr mode,Bool verbose,int flag)
 { {
     unsigned bw, bwMax, bpp;     unsigned bw, bwMax, bpp;
  
     bpp = (vgaBitsPerPixel + 1) / 8;     bpp = (vgaBitsPerPixel + 1) / 8;
     /*  
      * Set the bandwidth based upon the memory type.  
      */  
     bwMax = (ramType == BUFFER_SGRAM) ? 800000 : 700000;      bwMax = (ramType == 0 ) ? 800000 : 700000;
     /*  
      * Do a bandwidth calculation to see if this mode is safe.  
      */  
     bw = mode->Clock * bpp;     bw = mode->Clock * bpp;
     return (bw > bwMax ? MODE_BAD : MODE_OK);      return (bw > bwMax ? 255  : 0 );
 } }
  
  
Line 548 
Line 542 
  
 static void NV3FbInit(void) static void NV3FbInit(void)
 { {
   /* Need check in here for wierd resolutions !! */  
  
   if(!OFLG_ISSET(OPTION_SW_CURSOR, &vga256InfoRec.options)) {  
     /* Initialise the hardware cursor */    if(! ((  &vga256InfoRec.options )->flag_bits[( 62  )/ (8 * sizeof(CARD32)) ] & (1 << (( 62  )% (8 * sizeof(CARD32)) ))) ) {
     vgaHWCursor.Initialized = TRUE;  
       vgaHWCursor.Initialized = 1 ;
     vgaHWCursor.Init = NV3CursorInit;     vgaHWCursor.Init = NV3CursorInit;
     vgaHWCursor.Restore = NV3RestoreCursor;     vgaHWCursor.Restore = NV3RestoreCursor;
     vgaHWCursor.Warp = NV3WarpCursor;     vgaHWCursor.Warp = NV3WarpCursor;
     vgaHWCursor.QueryBestSize = NV3QueryBestSize;     vgaHWCursor.QueryBestSize = NV3QueryBestSize;
     if(xf86Verbose) {     if(xf86Verbose) {
       ErrorF("%s %s: %s: Using hardware cursor\n",XCONFIG_PROBED,        ErrorF("%s %s: %s: Using hardware cursor\n","(--)" ,
              vga256InfoRec.name,vga256InfoRec.chipset);              vga256InfoRec.name,vga256InfoRec.chipset);
     }     }
   }   }
  
   if(!OFLG_ISSET(OPTION_NOACCEL, &vga256InfoRec.options)) {    if(! ((  &vga256InfoRec.options )->flag_bits[( 60  )/ (8 * sizeof(CARD32)) ] & (1 << (( 60  )% (8 * sizeof(CARD32)) ))) ) {
     NVAccelInit();     NVAccelInit();
   }   }
  
Line 576 
Line 570 
 static Bool NV3ScreenInit(ScreenPtr pScreen,pointer pbits, static Bool NV3ScreenInit(ScreenPtr pScreen,pointer pbits,
                           int xsize,int ysize,int dpix,int dpiy,int width)                           int xsize,int ysize,int dpix,int dpiy,int width)
 { {
   return TRUE;    return 1 ;
 } }
  
 static void NV3SaveScreen(int on) static void NV3SaveScreen(int on)
Line 588 
Line 582 
 { {
 } }
  
 /* Changes the entries in the NV struct to point at the correct function  
  * pointers. Called from the Probe() function  
  */  
 static void NV3FlipFunctions(vgaVideoChipRec *nv) static void NV3FlipFunctions(vgaVideoChipRec *nv)
 { {
   nv->ChipEnterLeave=NV3EnterLeave;   nv->ChipEnterLeave=NV3EnterLeave;


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  Added in v.1.1.2.6

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